{"id":151,"date":"2021-11-09T01:47:16","date_gmt":"2021-11-09T01:47:16","guid":{"rendered":"https:\/\/asmeanlab.tech\/?page_id=151"},"modified":"2021-11-09T04:06:22","modified_gmt":"2021-11-09T04:06:22","slug":"red-pitaya-fpga-board-xilinx-zynq-7000","status":"publish","type":"page","link":"https:\/\/asmeanlab.tech\/?page_id=151","title":{"rendered":"Red Pitaya FPGA Board (Xilinx Zynq 7000)"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">Environment Setup<\/h2>\n\n\n\n<p>I&#8217;m using Vivado 2020.1 on a Ubuntu 18.04 distro.<\/p>\n\n\n\n<p>Red Pitaya&#8217;s repo is currently setup with all projects in 2020.1.  Do not use the newest version of Ubuntu, Vivado 2020.1 doesn&#8217;t run it it.  In addition, the C code development side seems to need SDK 2019.1 command line.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">FPGA Hardware Development<\/h2>\n\n\n\n<p>The code is all Verilog but pretty straightforward.  Builds are strightfoward and nicely the .bit is all that is needed, no conversion to a different file format for the device is needed.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>The filesystem is by default read-only.  To make r\/w<\/li><\/ul>\n\n\n\n<p><code>mount -o remount,rw \/opt\/redpitaya<\/code><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>To get the .bit from the fpga\/prj\/v0.94\/project\/redpitaya.runs\/impl_1 directory to the unit:<\/li><\/ul>\n\n\n\n<p><code>scp red_pitaya_top.bit root@<strong>ipaddress<\/strong>:\/tmp<\/code><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>To Reconfigure the FPGA while the unit is running:<\/li><\/ul>\n\n\n\n<p>SSH into the unit with <\/p>\n\n\n\n<p><code>ssh root@ipaddress<\/code><\/p>\n\n\n\n<p>Then configure the FPGA<\/p>\n\n\n\n<p><code>cat \/tmp\/red_pitaya_top.bit >\/dev\/xdevcfg<\/code><\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">FPGA\/SOC Interface Development<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">DTB File Update Procedure<\/h3>\n\n\n\n<p>At the moment, I haven&#8217;t changed any clocks or memory bus widths so I haven&#8217;t had to touch the DTB yet&#8230;.  <em>Update once I have&#8230;.<\/em><\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Linux C Development<\/h2>\n\n\n\n<p>I&#8217;m currently compiling the code on the device to avoid cross compiling.  <em>Update when I get cross compiling to work&#8230;.<\/em><\/p>\n\n\n\n<p><\/p>\n\n\n\n<h3 class=\"wp-block-heading\">API\/Library Development<\/h3>\n\n\n\n<p>The Linux to hardware interface is done through a memory mapped shared library (static also is built).<\/p>\n\n\n\n<p>I&#8217;ve made changes largely dealing with the WEA bits and the size of the buffers.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h3 class=\"wp-block-heading\">C Program Development<\/h3>\n\n\n\n<p>I&#8217;m currently using the SCPI connector software from Red Pitaya and modifying just as necessary.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>Notes:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>To start programs manually, set LD_LIBRARY_PATH first&#8230;.<\/li><\/ul>\n\n\n\n<p><code>LD_LIBRARY_PATH=\/opt\/redpitaya\/lib<br>export LD_LIBRARY_PATH<\/code><\/p>\n\n\n\n<p><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>The filesystem is by default read-only.  To make r\/w<\/li><\/ul>\n\n\n\n<p><code>mount -o remount,rw \/opt\/redpitaya<\/code><\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">VISA\/SCPI Control Software<\/h2>\n\n\n\n<p>I&#8217;m currently using MATLAB to send the command.  The things that commonly get me:<\/p>\n\n\n\n<ol class=\"wp-block-list\"><li>The SCPI Connector needs to be started in the Web GUI after startup<\/li><li>The TCP\/IP buffer needs to be made bigger to send waveforms.<\/li><\/ol>\n\n\n\n<p>Any program\/language capable of sending strings over TCP\/IP would work here&#8230;.<\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Environment Setup I&#8217;m using Vivado 2020.1 on a Ubuntu 18.04 distro. Red Pitaya&#8217;s repo is currently setup with all projects in 2020.1. Do not use the newest version of Ubuntu, Vivado 2020.1 doesn&#8217;t run it it. In addition, the C code development side seems to need SDK 2019.1 command line. FPGA Hardware Development The code [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":40,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-151","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/pages\/151","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=151"}],"version-history":[{"count":16,"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/pages\/151\/revisions"}],"predecessor-version":[{"id":167,"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/pages\/151\/revisions\/167"}],"up":[{"embeddable":true,"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=\/wp\/v2\/pages\/40"}],"wp:attachment":[{"href":"https:\/\/asmeanlab.tech\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=151"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}